• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    A negative impedance circuit comprises:- a differential circuit stage (10) having a first input, a second input and an output,- a positive feedback path (A) from the output to the first input of the differential circuit stage (10),- a negative feedback path (B) from the output to the second input of the differential circuit stage (10) .The negative feedback path (B) comprises a unitary gain path from the output to the second input of the differential circuit stage (10), the unitary gain path being coupled to ground (GND) via a reference impedance (Z<sub>REF</sub>).The negative feedback path (B) and the positive feedback path (A) comprise a first transistor (M1) and a second transistor (M2) having respective control electrodes driven by the output of the differential circuit stage (10) with the first transistor (M1) and the second transistor (M2) coupled in a current mirror arrangement, wherein a negative impedance (Z<sub>NEG</sub>) is available at the first input of the differential circuit stage (10).
    公开号:EP3683963A1
    申请号:EP20151228.2
    申请日:2020-01-10
    公开日:2020-07-22
    发明作者:Mr. Andrea BARBIERI；Mr. Aldo VIDONI
    申请人:STMicroelectronics SRL；
    IPC主号:H03H11-00
    专利说明:
    [0001] The description relates to negative impedance circuits.
    [0002] One or more embodiments may be applied to various types of devices such as, for instance, read interfaces for ultrasound probes and the like.
    [0003] Read interfaces for Piezoelectric Micro-machined Ultrasonic Transducers (PMUTs) are exemplary of a possible field of application of embodiments. Technological background
    [0004] Various types of analog circuits benefit from the possible use of negative impedance circuits.
    [0005] Also, various types of arrangements are known and adopted for providing negative impedance circuits.
    [0006] Circuits jointly adopting positive and negative feedback are exemplary of such arrangements: for instance, so-called negative capacitance converters are known wherein a high negative capacitance may be implemented in a process involving low-density capacitors.
    [0007] These known arrangements may exhibit limitations related, for instance, to an undesirably high ratio of the resistances included in the negative feedback path which may translate into a limitation in the input signal dynamics. Object and summary
    [0008] An object of one or more embodiments is to contribute in providing further improvements in negative impedance circuits by overcoming the drawbacks outlined in the foregoing.
    [0009] According to one or more embodiments, that object may be achieved by means of a negative impedance circuit having the feature set forth in the claims that follow.
    [0010] One or more embodiments may relate to a corresponding device.
    [0011] A PMUT reading interface may be exemplary of such a device.
    [0012] The claims are an integral part of the technical disclosure provided herein in connection with embodiments. Brief description of the figures
    [0013] One or more embodiments will now be described, by way of example only, with reference to the annexed figures, wherein:Figure 1 is a diagram exemplary of a possible use of negative impedance circuits, Figures 2 and 3 are circuits diagrams exemplary of negative impedance circuits, Figures 4 and 5 are circuit diagrams exemplary of negative impedance circuits of embodiments of the present description, Figures 6 and 7 are circuit diagrams exemplary of possible transistor-level implementations of embodiments of the present description, and Figure 8 is a block diagram exemplary of a possible use of embodiments as exemplified herein. Detailed description of examples of embodiments
    [0014] In the ensuing description, one or more specific details are illustrated, aimed at providing an in-depth understanding of examples of embodiments of this description. The embodiments may be obtained without one or more of the specific details, or with other methods, components, materials, etc. In other cases, known structures, materials, or operations are not illustrated or described in detail so that certain aspects of embodiments will not be obscured.
    [0015] Reference to "an embodiment" or "one embodiment" in the framework of the present description is intended to indicate that a particular configuration, structure, or characteristic described in relation to the embodiment is comprised in at least one embodiment. Hence, phrases such as "in an embodiment" or "in one embodiment" that may be present in one or more points of the present description do not necessarily refer to one and the same embodiment. Moreover, particular conformations, structures, or characteristics may be combined in any adequate way in one or more embodiments.
    [0016] The references used herein are provided merely for convenience and hence do not define the extent of protection or the scope of the embodiments.
    [0017] Also, throughout this description, certain circuit nodes and the signals at these nodes will be indicated with same reference (Vx, VOUT, ...) for simplicity and ease of explanation.
    [0018] The diagram of Figure 1 is exemplary of certain electronic devices wherein a block or cell AC may exhibit a low input impedance ZIN: this may be undesirable as possibly representing the source of various issues in device design and operation.
    [0019] A known approach to address such issues involves coupling to the (low) impedance ZIN a "negative" impedance ZNEG (-ZNEG) so that the input impedance V'X/I'X "seen" towards the cell AC may be expressed as Z IN , EQ + Vʹ X / ʹ I X = Z NEG Z IN / Z NEG − Z IN
    [0020] In that way, an undesirably low impedance ZIN can be converted to a higher impedance value as a result of being multiplied by the ratio ZNEG/(ZNEG-ZIN) with (ZNEG-ZIN) providing a small value for the denominator of the ratio ZNEG/(ZNEG-ZIN).
    [0021] Figures 2 and 3 are exemplary of possible approaches in obtaining a negative impedance ZNEG = VX/IX by resorting to a differential stage 10 (an operational amplifier or op-amp may be exemplary of such a differential stage) with the joint use of positive feedback (loop A - indicated with a continuous line) and negative feedback (loop B - indicated with a dashed line).
    [0022] For instance, in an arrangement as exemplified in Figure 2, the output terminal of the differential stage 10 is coupled via a feedback impedance ZPFB to the non-inverting input of the differential stage 10 (considered as the input node to the circuit, where input voltage Vx and current Ix are present) thus providing a positive feedback path A.
    [0023] The output from the stage 10 is also coupled to the inverting input of the differential stage 10 via a voltage divider.
    [0024] Such a voltage divider may be provided by a first resistor R1 (lower branch of the voltage divider, between the inverting input of the stage 10 and ground GND) and a second resistor R2 (upper branch of the voltage divider, between the output and the inverting input of the differential stage 10).
    [0025] In an arrangement as exemplified in Figure 2, the output voltage VOUT from the differential stage 10 can be expressed as V OUT = 1 + R 2 / R 1 V X
    [0026] Figure 3 is exemplary of the possibility of implementing an arrangement as represented in Figure 2 by using a capacitance CFB as the feedback impedance ZPFB.
    [0027] In an arrangement as exemplified in Figure 3 the following relationships will apply: Z NEG = V X / I X = − 1 / sC FB R 1 / R 2
    [0028] Implementing an arrangement as exemplified in Figure 3 in order to provide a high negative capacitance in a process with low-density capacitors involves high values for the ratio R2/R1.
    [0029] With VOUT = (1 + R2/R1)VX, selecting a high value for R2/R1 leads to the dynamics of the signal VOUT being (much) higher than the dynamics for the input signal Vx. This in turn results in an undesired limitation in the input dynamics based on the relationship V X , MAX = V OUT , MAX / 1 + R 2 / R 1 .
    [0030] In embodiments as exemplified in Figure 4, parts or elements like parts or elements already discussed in connection with the previous figures are indicated with like reference symbols, so that a detailed description will not be repeated for brevity.
    [0031] In one or more embodiments as generally exemplified in Figure 4 the negative feedback path B from the output terminal of the differential stage 10 to the non-inverting input of the differential stage 10 is implemented without voltage amplification, that is with the output voltage of the differential stage 10, namely VOUT, caused to be substantially equal to the input voltage VX to the circuit with a reference impedance ZREF between the inverting input of the differential stage 10 and ground GND.
    [0032] For the sake of completeness and ease of understanding, in Figure 4 (the same also applies to Figure 5) current generators IOUT are also illustrated in order to show that, in embodiments as exemplified herein, an operational amplifier or OpAmp including two or more stages may be used where the triangle designated 10 can be regarded as exemplary of the first (differential) amplifier stage, while the transistor M1 and the respective current generator represent the output stage.
    [0033] In embodiments as exemplified in Figure 4: the (negative) feedback path B coupling the output terminal from the differential stage 10 to the non-inverting input of the differential stage 10 comprises a first transistor M1, and the (positive) feedback path A coupling the output terminal from the differential stage 10 to the inverting input of the differential stage 10 comprises a second transistor M2, the transistors M1 and M2, whose control electrodes (gates, in the case of field-effect transistors such as MOSFETs as exemplified herein) are included in a 1:M current mirror so that a current IREF flows through M1 and ZREF while the current MIREF through M2 corresponds to -Ix.
    [0034] In an arrangement as exemplified in Figure 4 (and the same may also apply to arrangements as exemplified in the following figures) a positive feedback path A may be provided which couples the output terminal from the differential stage 10 to the inverting input of the differential stage 10, while a negative feedback path B may be provided which couples the output terminal from the differential stage 10 to the non-inverting input of the differential stage 10. Such an arrangement takes into account the fact that, in arrangements as exemplified herein) output stages such as M1 (current IOUT) in Figure 4 and 5 or 10A-10B in Figure 6 are inverting stages.
    [0035] That is, to provide a positive feedback the differential stage 10 in Figures 4 and 5 and Figure 6 (as discussed in the following) are shown with "reversed" inputs.
    [0036] Those of skill in the art will appreciate that the coupling options to the inverting/non-inverting inputs of the differential stage 10 as exemplified herein are related to the inverting behavior of the associated output stages. Consequently, coupling options as exemplified herein are not per se mandatory; one or more embodiments may thus adopt different coupling options, for instance, complementary coupling options (inverting >>> non-inverting, non-inverting >>> inverting) in order to provide positive and negative feedback paths as desired.
    [0037] In an arrangement as exemplified in Figure 4, the transistors M1, M2 of the current mirror are exemplified in the form of MOSFETs having mutually-coupled control terminals (gates) jointly coupled to the output terminal of the differential stage 10.
    [0038] As discussed, in an arrangement as exemplified in Figure 4, the current paths (source/drain, in the case of field effect transistors such as MOSFETs) of the transistors M1 and M2 extend between a supply terminal VDD and the non-inverting and inverting inputs, respectively, to the differential stage 10 so that a current IREF will flow through M1 and ZREF, while the current MIREF through M2 corresponds to -Ix.
    [0039] In an arrangement as exemplified in Figure 4 the following relationships will apply: I REF = V X / Z REF
    [0040] In Figure 5, parts or elements like parts or elements already discussed in connection with the previous figures are again indicated with like symbols, so that a corresponding description will not be repeated for brevity.
    [0041] Figure 5 is exemplary of an arrangement where the general circuit layout exemplified in Figure 4 is implemented by using a reference capacitance CREF as the reference impedance ZREF coupled between the non-inverting input of the differential stage 10 and ground GND.
    [0042] In an arrangement as exemplified in Figure 5, the following relationships will apply: Z NEG = V X / I X = − 1 / sC REF M
    [0043] Where, again, s = jω (ω = angular frequency) and no voltage amplification is pursued so that V X , MAX = V OUT , MAX
    [0044] As discussed previously, Figures 4 and 5 are exemplary of embodiments which adopt an operational amplifier including two (or more) stages where the triangle designated 10 can be regarded as exemplary of a first (differential) amplifier stage, while the transistor M1 and the respective current generator represent a corresponding output stage.
    [0045] In Figures 6 and 7, parts or elements like parts or elements already discussed in connection with the previous figures are again indicated with like symbols, so that a corresponding description will not be repeated for brevity.
    [0046] Figures 6 and 7 are exemplary of possible implementations wherein the reference impedance ZREF (this may include a reference capacitance CREF: a generic impedance ZREF is shown in Figures 6 and 7 to provide a more comprehensive representation) is coupled to the negative feedback path B at an output node O from the differential stage 10 arranged intermediate two output transistors 10A, 10B (MOSFETs are again referred to as an example) having their current paths (source/drain, in the case of the field-effect transistors such as MOSFETs) cascaded - that is, essentially in series - between a supply node again designated VDD and ground GND.
    [0047] As shown in Figures 6 and 7, the transistors 10A, 10B have their control terminals (gates, in the case of field-effect transistors such as MOSFETs as exemplified herein) coupled to respective outputs of an input stage 100 in a current mirror operational transconductance amplifier or OTA providing the differential core of the stage 10. The dual outputs of the differential input stage 100 are in phase (that is are identical in terms of ac component) while also providing a correct DC bias for the (MOSFET) transistors 10A and 10B.
    [0048] For the sake of completeness one may note that the implementation of Figure 6 includes a current mirror OTA with the (MOSFET) transistors 10A e 10B representing output transistors and the triangle 100 representing the differential input stage. Using such an amplifier to provide a negative impedance is a point of interest of embodiments.
    [0049] In embodiments as exemplified in Figures 6 and 7, the positive feedback path is split into two branches namely: a first branch A1 from one of the output nodes of the differential input stage 100 to the control electrode of the transistor 10A and on to the non-inverting input (Vx, Ix) of the differential stage 10 (that is, to the inverting input of the differential input stage 100) via a first transistor 10C, and a second branch A2 from the other of the output nodes of the differential input stage 100 to the control electrode of the transistor 10B and on to the non-inverting input (Vx, Ix) of the differential stage 10 (that is to the inverting input of the differential input stage 100) via a second transistor 10D.
    [0050] Splitting the positive feedback path A into two branches A1, A2 is related to the use of a current mirror OTA as exemplified herein. This was found to provide an appreciable improvement in terms of frequency response in comparison to implementations using, for instance, a standard two-stage OpAmp.
    [0051] An alternative approach, still providing satisfactory bandwidth performance, may involve using a two-stage OpAmp as exemplified in Figure 4 and Figure 5, with the block 10 and the (e.g. MOSFET) transistor M1 plus the generator lout as the input stage and the output stage, respectively.
    [0052] As exemplified in Figures 6 and 7, the transistors 10C, 10D (MOSFETs are once more referred to by way of example) are arranged with their current paths (source/drain in the case of field-effect transistors such as MOSFETs) between, respectively: the supply terminal VDD and the non-inverting input of the differential stage 10 (the inverting input of the differential input stage 100), that is the input node at which VX is applied, and the input node at which VX is applied, that is the non-inverting input to the differential stage 10 (the inverting input of the differential input stage 100), and ground GND.
    [0053] In an arrangement as exemplified in Figure 6, the transistors 10A and 10C (on the one hand) and transistors 10B and 10D (on the other hand) provide respective current mirror arrangements 10A, 10C and 10B, 10D just like the 1:M current mirror arrangements exemplified by the transistors M1 and M2 in the more general representations of Figures 4 and 5.
    [0054] The transistor-level circuit representation of Figure 7 further details a possible implementation of the differential input stage 100 (including four transistors 100A, 100B, 100C, 100D) and a tail current generator 2IB with two current paths between the supply terminal VDD and ground GND via the current paths through transistors 100A, 100B and transistors 100C, 100D, respectively.
    [0055] In Figure 7 two further transistors 10E, 10F are shown (again MOSFETs are referred to for simplicity), the latter in a diode arrangement, so that - in a current mirror amplifier as considered herein - the transistors 100C, 10E and 10F mirror the current of the input transistor 100D into the output transistor 10D and the transistor 100A mirrors the current through the input transistor 100B into the output transistor 10C.
    [0056] In Figure 7 also currents IB + IL/2 and IB - IL/2 are shown flowing from the transistor 10A towards the node O and from the node O towards the transistor 10B, respectively.
    [0057] These currents are mirrored by currents M (IB + ID/2) and M (IB - IL/2) flowing from the transistor 10C to the input node to which the voltage VX is applied and from that node towards the transistor 10D resulting in a current MIREF flowing at the input terminal VX.
    [0058] It will be appreciated that in Figure 7 the current MIREF is represented (on the right hand-side of the figure) with an arrow pointing towards the outside of the node VX, that is as a current flowing from the circuit in the presence of an assumed positive voltage VX: this exemplifies the negative impedance behavior of the circuit exemplified (that is the negative impedance which may be "seen" at that node).
    [0059] Those of skill in the art will again appreciate that the coupling options to the inverting/non-inverting inputs of the differential input stage 100 as exemplified herein are related to the inverting behavior of the associated output stages. Consequently, coupling options as exemplified herein are not per se mandatory; one or more embodiments may thus adopt different coupling options, for instance, complementary coupling options (inverting >>> non-inverting, non-inverting >>> inverting) in order to provide positive and negative feedback paths as desired.
    [0060] Figure 8 is exemplary of a possible use of a plurality (in fact any number) of circuits providing a negative impedance ZNEG as exemplified in Figures 4 through 7 within the framework of a PMUT reading interface 200.
    [0061] In Figure 8, reference 202 denotes as a whole a PMUT array with the PMUTs in the array coupled to respective amplifiers 204 (low-noise amplifiers or LNAs, for instance) whose outputs are applied to respective analog delay circuits collectively designated 206 intended to perform a beamforming action and whose outputs are supplied to an adder 208 to provide an output signal as desired.
    [0062] The general architecture of the interface 200 in Figure 8 is per se known to those of skill in the art, which makes it unnecessary to provide a more detailed description herein.
    [0063] In such interface architecture, each delay block in the set 206 can be regarded as a capacitive load to an associated LNA 204, with such a capacitive load possibly reducing the bandwidth of the LNA. Coupling between each LNA 204 and the associated delay block 206 a negative impedance ZNEG comprising a negative capacitance in parallel to the input capacitance of the delay block (see Figure 1, for instance) will cause the negative capacitance to subtract from the input capacitance of the delay block and the resulting smaller capacitance will translate into increased LNA bandwidth.
    [0064] Due to voltage amplification being dispensed with (namely with VX,MAX = VOUT,MAX as exemplified herein) output signal dynamics will not be limited as may possibly happen in the case of conventional solutions.
    [0065] A circuit as exemplified herein may comprise: a differential circuit stage (see, for instance, 10, possibly including a differential input stage 100) having a first input (see, for instance, the non-inverting input of the stage 10 as possibly provided by the inverting input node of the differential input stage 100), a second input (see, for instance, the inverting input of the stage 10 as possibly provided by the non-inverting input node of the differential input stage 100) and an output (see, for instance, the output from the stage 10 as possibly provided as a dual output comprising the first and second output nodes of the differential input stage 100), at least one positive feedback path (for instance, A in Figures 4 and 5 or A1, A2 in Figures 6 and 7) from the output to the first input of the differential circuit stage, a negative feedback path (for instance, B) from the output to the second input of the differential circuit stage, wherein: the negative feedback path comprises a unitary gain path from the output to the second input of the differential circuit stage, the unitary gain path coupled to ground (e.g., GND) via a reference impedance (for instance ZREF or CREF), the negative feedback path and the at least one positive feedback path comprise a first transistor (for instance, M1 in Figures 4 and 5 or 10A, 10B in Figures 6 and 7) and a second transistor (for instance, M2 in Figures 4 and 5 or 10C, 10D in Figures 6 and 7), respectively, the first transistor and the second transistor having respective control electrodes (for instance gates, in the case of field-effect transistors such as MOSFETs) driven by the output of the differential circuit stage, the first transistor and the second transistor coupled in a current mirror arrangement, wherein a negative impedance (for instance, ZNEG or CIN) is available at the first input (for instance Vx) of the differential circuit stage.
    [0066] In a circuit as exemplified herein, the reference impedance may comprise a capacitive impedance (for instance, CREF)wherein the negative impedance (for instance CIN) available at the first input of the differential circuit stage (for instance, Vx) may comprise a negative capacitive impedance.
    [0067] In a circuit as exemplified herein, the first transistor (for instance, M1 in Figures 4 and 5 or 10A, 10B in Figures 6 and 7) and the second transistor (for instance, M2 in Figures 4 and 5 or 10C, 10D in Figures 6 and 7) may be coupled in a current mirror arrangement having a current gain, M (for instance, with M higher than 1), from the first transistor to the second transistor.
    [0068] In a circuit as exemplified herein: the differential circuit stage may comprise a differential input stage (for instance, 100) having a first input node, a second input node and a dual output comprising a first output node and a second output node, a first positive feedback path (for instance, A1) may be provided from the first output node to the first input node of the differential input stage, a second positive feedback path (for instance, A2) may be provided from the second output node to the first input node of the differential input stage, the negative feedback path may be provided to the second input node of the differential input stage from a feedback node (for instance O) coupled to both the first output node and the second output node in the dual output of the differential input stage via respective first transistors in a pair of first transistors (for instance 10A, 10B in Figures 6 and 7), the first positive feedback path and the second positive feedback path may comprise respective second transistors in a pair of second transistors (for instance 10C, 10D in Figures 6 and 7), each of the first transistors in the pair of first transistors may be coupled in a current mirror arrangement to a respective one of the second transistors in the pair of second transistors (that is, for instance 10A with 10C and 10B with 10D) wherein a negative impedance is available at the first input node (for instance Vx) of the differential circuit stage.
    [0069] In a circuit as exemplified herein, said transistors (for instance M1, M2 or 10A, 10B, 10C, 10D) may comprise MOSFETs.
    [0070] An electronic device (for instance, 200) as exemplified herein may comprise: at least one circuit block (for instance, 206) exhibiting an input impedance, at least one circuit as exemplified herein arranged with the first input (for instance, Vx) of the differential circuit stage coupled to said at least one circuit block wherein said input impedance is modified as a function of said negative impedance available at the first input of the differential circuit stage.
    [0071] In an electronic device as exemplified herein, the input impedance of the at least one circuit block and said negative impedance available at the first input of the differential circuit stage may comprise capacitive impedances.
    [0072] An electronic device as exemplified herein may comprise an ultrasonic transducer read interface comprising at least one (e.g., beamforming) circuit module (for instance, 206) having a input node configured to receive a ultrasonic transducer signal from an ultrasonic transducer (for instance, 202), with said at least one circuit arranged with the first input of the differential circuit stage coupled to said input node of the at least one circuit module.
    [0073] Without prejudice to the underlying principles, the details and embodiments may vary, even significantly, with respect to what has been described herein by way of example only, without departing from the scope of protection.
    [0074] The scope of protection is determined by the claims that follow.
    权利要求:
    Claims (8)
    [0001] A circuit, comprising:
    - a differential circuit stage (10, 100) having a first input, a second input and an output,
    - at least one positive feedback path (A; A1, A2) from the output to the first input of the differential circuit stage (10, 100),
    - a negative feedback path (B) from the output to the second input of the differential circuit stage (10, 100),wherein:
    - the negative feedback path (B) comprises a unitary gain path from the output to the second input of the differential circuit stage (10, 100), the unitary gain path coupled to ground (GND) via a reference impedance (ZREF; CREF),
    - the negative feedback path (B) and the at least one positive feedback path (A; A1, A2) comprise a first transistor (M1; 10A, 10B) and a second transistor (M2; 10C, 10D), respectively, the first transistor (M1; 10A, 10B) and the second transistor (M2; 10C, 10D) having respective control electrodes driven by the output of the differential circuit stage (10, 100), the first transistor (M1; 10A, 10B) and the second transistor (M2; 10C, 10D) coupled in a current mirror arrangement, wherein a negative impedance (ZNEG; CIN) is available at the first input of the differential circuit stage (10, 100) .
    [0002] The circuit of claim 1, wherein the reference impedance comprises a capacitive impedance (CREF) wherein the negative impedance (CIN) available at the first input of the differential circuit stage (10, 100) comprises a negative capacitive impedance.
    [0003] The circuit of claim 1 or claim 2, wherein the first transistor (M1; 10A, 10B) and the second transistor (M2; 10C, 10D) are coupled in a current mirror arrangement having a current gain, M, from the first transistor (M1; 10A, 10B) to the second transistor (M2; 10C, 10D).
    [0004] The circuit of any of the previous claims, wherein:
    - the differential circuit stage (10) comprises a differential input stage (100) having a first input node, a second input node and a dual output comprising a first output node and a second output node,
    - a first positive feedback path (A1) is provided from the first output node to the first input node of the input differential stage (100),
    - a second positive feedback path (A2) is provided from the second output node to the first input node of the input differential stage (100),
    - the negative feedback path (B) is provided to the second input node of the input differential stage (100) from a feedback node (O) coupled to both the first output node and the second output node in the dual output of the input differential stage (100) via respective first transistors in a pair of first transistors (10A, 10B),
    - the first positive feedback path (A1) and the second positive feedback path (A2) comprise respective second transistors in a pair of second transistors (10C, 10D),
    - each of the first transistors in the pair of first transistors (10A, 10B) is coupled in a current mirror arrangement to a respective one of the second transistors in the pair of second transistors (10C, 10D) wherein a negative impedance (ZNEG) is available at the first input node of the differential circuit stage (10, 100).
    [0005] The circuit of any of the previous claims, wherein said transistors (M1, M2; 10A, 10B, 10C, 10D) comprise MOSFETs.
    [0006] An electronic device (200), comprising:
    - at least one circuit block (206) exhibiting an input impedance (ZIN),
    - at least one circuit according to any of the previous claims arranged with the first input of the differential circuit stage (10, 100) coupled to said at least one circuit block (206) wherein said input impedance (ZIN) is modified as a function of said negative impedance (ZNEG; CIN) available at the first input of the differential circuit stage (10, 100).
    [0007] The electronic device (200) of claim 6, wherein the input impedance of the at least one circuit block (206) and said negative impedance (CIN) available at the first input of the differential circuit stage comprise capacitive impedances.
    [0008] The electronic device (200) of claim 6 or claim 7, wherein the device comprises an ultrasonic transducer read interface comprising at least one circuit module (206) having a input node configured to receive a ultrasonic transducer signal from an ultrasonic transducer (202), with said at least one circuit arranged with the first input of the differential circuit stage (10, 100) coupled to said input node of the at least one circuit module (206).
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    同族专利:
    公开号 | 公开日
    CN111464150A|2020-07-28|
    US20200230648A1|2020-07-23|
    CN211908756U|2020-11-10|
    引用文献:
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